Since the debut of Multi-chip Modules (MCM), many research and development works have brought the technology from the physical design, test to mass production, but still lacking thermal data to support the schematic designs; especially in the area of thermal design related junction temperature. This method proposes a new approach to implant the temperature sensor into the MCM thus to sense the substrate and to probe the junction temperature. Further, to explore the possibility of using the IEEE1149.7 based cJTAG of the function test in conjunction of the IEEE1149.1 based boundary scan test coherently. This method is to activate a pair of I2C bus as per SCL/SDA lines and to drive and sense the master chip in response of its slave chip. The test platform used in this proposal is to apply the JTAG Technologies based Provision and Core-commander test systems, both of which working together to trouble-shooting and debugging. This is accomplished through manipulating the core logic of the customized IP code amid the Python functions in order to retract the temperature reading from the sensor via the I2C bus. Both JTAG and cJTAG use the common netlist and BSDL files (Boundary Scan Descriptive Language) to generate the test files and firmware coding through the JTAG’s Test Access Port (TAP). The formula implemented here has its theoretic roots in a function of the resistance networks which equal to the temperature difference over the the heat flow. This development work uses the high-level GUI language from the core-commander to instruct the Python based functional calls invoking the device drivers, and that has greatly simplified the complex electronic designs with reduced programming, and this exercise has obtained the junction temperature presumably at 71 degrees C on the threshold of temperature gradients, and it’s one step closer towards the case temperature from the thermal management point of view.
Published in | Journal of Electrical and Electronic Engineering (Volume 10, Issue 2) |
DOI | 10.11648/j.jeee.20221002.11 |
Page(s) | 39-46 |
Creative Commons |
This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited. |
Copyright |
Copyright © The Author(s), 2022. Published by Science Publishing Group |
Boundary Scan Test, Multi-chip Module, Thermal Management, Automotive Electronics, JTAG
[1] | Wang Shun Shen Peter “Instrumentation of Twin-MUM based Mutual Test”, published by “Microelectronics Journal”, Vol. 114 on August 21, 2021, http://doi.org.j.mejo.2021.105108. |
[2] | Wang Shun Shen Peter, IEEE/International Test Conference, Washington D.C. 2020, Nov. 6-10, published on http://dx.doi.org/10.6180/, “Switch Mode Interposer developed to self-test an MCM without Known Good Dice”. |
[3] | Wang, Shun Shen Peter, “Switch-Mode based interposer enabling Self-Testing of an MCM without Known-Good-Die” U.S. Patent Pending No. 17240956. |
[4] | Harry Bleeker and Peter van den Eijnden: “Boundary Scan Test A Practical Approach”, published book by Eluwer Academic, Netherlands @1993. |
[5] | G. N. Lison, “Thermal Computations for Electronics Equipment”, Published by Van Nostrend Reinhold Company, Inc. 1984. |
[6] | Data sheet: “AN5375, The S32R27x is a 32-bit Power Architecture® based Micro-controller Unit (MCU) targeted for automotive applications.” |
[7] | Data sheet: “NXP SoCs: strike the optimal performance-per-watt balance for hardware-accelerated, high-resolution RADAR systems designed for safer, smarter vehicle.” |
[8] | https://www.jtag.com. |
[9] | IBM Research Report, RC24582 (W0806-039) June 11, 2008 Material Science. |
[10] | The Leading Edge of Production: “Wafer Probe Test Technology, IEEE/ITC Oct. 26-28 2004 pp. 1.4.1168”. |
[11] | TSMC Demonstration a “7nM ARM-based chip let Design for HPC, 2019 VLSI Technology Symposium, Kyoto, Japan”. |
[12] | P.M. Gammen, Wafer Scale Integration US Patent 4,866.501, “Design and Fabrication of Silicon-on-Silicon-Carbine”, School of Engineering, University of Warwick, Cenventy, UK, E3S Web of Conference 16, 12003 (2017). |
[13] | The Leading Edge of “Production Wafer Probe Test Technology”, IEEE/ITC, OCT.26-28 2004 PP. 41.4.1168. |
[14] | C.A. Bower, “High Density Vertical Interference for 3-D Integration of Silicon Integrated Circuits, IEEE Electronics and Components and Technology Conference” (2006). |
[15] | “Multi-channel MCM with Test Circuitry for Inter-die bond wire checking”, Texas Instrument, May 25, 2016. |
[16] | Perceval Coudrain , etc. , “Active Interposer advanced system architecture”, 2019”, 69th Electronic Components and Technology Conference (ECTC), pp 569-578. |
[17] | Wang Shun Shen Peter, Chee Cheong Wong “Wafer Scale Burn-in Testing”, Patent No. 6,121,065, assignee: Institute of Microelectronics, Singapore, Singapore, issued date: Sep.19, 2000. |
APA Style
Wang Shun Shen Peter, Wang Yin Tien, Chao Chong Lii, Yang Wei Bin, Wu Chyan Chyi, et al. (2022). Thermal Design of an MCM with the Implanted Temperature Sensor. Journal of Electrical and Electronic Engineering, 10(2), 39-46. https://doi.org/10.11648/j.jeee.20221002.11
ACS Style
Wang Shun Shen Peter; Wang Yin Tien; Chao Chong Lii; Yang Wei Bin; Wu Chyan Chyi, et al. Thermal Design of an MCM with the Implanted Temperature Sensor. J. Electr. Electron. Eng. 2022, 10(2), 39-46. doi: 10.11648/j.jeee.20221002.11
AMA Style
Wang Shun Shen Peter, Wang Yin Tien, Chao Chong Lii, Yang Wei Bin, Wu Chyan Chyi, et al. Thermal Design of an MCM with the Implanted Temperature Sensor. J Electr Electron Eng. 2022;10(2):39-46. doi: 10.11648/j.jeee.20221002.11
@article{10.11648/j.jeee.20221002.11, author = {Wang Shun Shen Peter and Wang Yin Tien and Chao Chong Lii and Yang Wei Bin and Wu Chyan Chyi and Lee Tzung Hang}, title = {Thermal Design of an MCM with the Implanted Temperature Sensor}, journal = {Journal of Electrical and Electronic Engineering}, volume = {10}, number = {2}, pages = {39-46}, doi = {10.11648/j.jeee.20221002.11}, url = {https://doi.org/10.11648/j.jeee.20221002.11}, eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.20221002.11}, abstract = {Since the debut of Multi-chip Modules (MCM), many research and development works have brought the technology from the physical design, test to mass production, but still lacking thermal data to support the schematic designs; especially in the area of thermal design related junction temperature. This method proposes a new approach to implant the temperature sensor into the MCM thus to sense the substrate and to probe the junction temperature. Further, to explore the possibility of using the IEEE1149.7 based cJTAG of the function test in conjunction of the IEEE1149.1 based boundary scan test coherently. This method is to activate a pair of I2C bus as per SCL/SDA lines and to drive and sense the master chip in response of its slave chip. The test platform used in this proposal is to apply the JTAG Technologies based Provision and Core-commander test systems, both of which working together to trouble-shooting and debugging. This is accomplished through manipulating the core logic of the customized IP code amid the Python functions in order to retract the temperature reading from the sensor via the I2C bus. Both JTAG and cJTAG use the common netlist and BSDL files (Boundary Scan Descriptive Language) to generate the test files and firmware coding through the JTAG’s Test Access Port (TAP). The formula implemented here has its theoretic roots in a function of the resistance networks which equal to the temperature difference over the the heat flow. This development work uses the high-level GUI language from the core-commander to instruct the Python based functional calls invoking the device drivers, and that has greatly simplified the complex electronic designs with reduced programming, and this exercise has obtained the junction temperature presumably at 71 degrees C on the threshold of temperature gradients, and it’s one step closer towards the case temperature from the thermal management point of view.}, year = {2022} }
TY - JOUR T1 - Thermal Design of an MCM with the Implanted Temperature Sensor AU - Wang Shun Shen Peter AU - Wang Yin Tien AU - Chao Chong Lii AU - Yang Wei Bin AU - Wu Chyan Chyi AU - Lee Tzung Hang Y1 - 2022/03/04 PY - 2022 N1 - https://doi.org/10.11648/j.jeee.20221002.11 DO - 10.11648/j.jeee.20221002.11 T2 - Journal of Electrical and Electronic Engineering JF - Journal of Electrical and Electronic Engineering JO - Journal of Electrical and Electronic Engineering SP - 39 EP - 46 PB - Science Publishing Group SN - 2329-1605 UR - https://doi.org/10.11648/j.jeee.20221002.11 AB - Since the debut of Multi-chip Modules (MCM), many research and development works have brought the technology from the physical design, test to mass production, but still lacking thermal data to support the schematic designs; especially in the area of thermal design related junction temperature. This method proposes a new approach to implant the temperature sensor into the MCM thus to sense the substrate and to probe the junction temperature. Further, to explore the possibility of using the IEEE1149.7 based cJTAG of the function test in conjunction of the IEEE1149.1 based boundary scan test coherently. This method is to activate a pair of I2C bus as per SCL/SDA lines and to drive and sense the master chip in response of its slave chip. The test platform used in this proposal is to apply the JTAG Technologies based Provision and Core-commander test systems, both of which working together to trouble-shooting and debugging. This is accomplished through manipulating the core logic of the customized IP code amid the Python functions in order to retract the temperature reading from the sensor via the I2C bus. Both JTAG and cJTAG use the common netlist and BSDL files (Boundary Scan Descriptive Language) to generate the test files and firmware coding through the JTAG’s Test Access Port (TAP). The formula implemented here has its theoretic roots in a function of the resistance networks which equal to the temperature difference over the the heat flow. This development work uses the high-level GUI language from the core-commander to instruct the Python based functional calls invoking the device drivers, and that has greatly simplified the complex electronic designs with reduced programming, and this exercise has obtained the junction temperature presumably at 71 degrees C on the threshold of temperature gradients, and it’s one step closer towards the case temperature from the thermal management point of view. VL - 10 IS - 2 ER -